--
-- CSSE2000 8 Bit Microprocessor
-- Copyright (C) 2011 Nathan Rossi (University of Queensland)
--
-- THIS DESIGN/CODE IS PROVIDED TO YOU UNDER THE FOLLOWING LICENSE:
--
-- All material is restricted to use in the CSSE2000 Project for 2011.
-- You may not redistribute the file/code/design, without the consent of the author.
--

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library work;
use work.proc_package.ALL;

entity proc_alu is
	port (
		clk : in std_logic;
		rst : in std_logic;
		en : in std_logic;
		
		mode : in PROC_ALU_MODE;
		
		-- Inputs
		status_in : in PROC_REG_DATA_TYPE;
		a : in PROC_REG_DATA_TYPE;
		b : in PROC_REG_DATA_TYPE;
		
		-- Outputs
		result : out PROC_REG_DATA_TYPE;
		status_out : out PROC_REG_DATA_TYPE
	);
end proc_alu;

architecture Behavioral of proc_alu is
	
	component proc_alu_netlist port (
		clk : in std_logic;
		rst : in std_logic;
		en : in std_logic;
		
		mode : in std_logic_vector(3 downto 0);
		
		-- Inputs
		status_in : in PROC_REG_DATA_TYPE;
		a : in PROC_REG_DATA_TYPE;
		b : in PROC_REG_DATA_TYPE;
		
		-- Outputs
		result : out PROC_REG_DATA_TYPE;
		status_out : out PROC_REG_DATA_TYPE
	); end component;
	
	signal s_mode : std_logic_vector(3 downto 0);
begin
	
	-- When implementing the ALU, remove this instance
	s_mode <= alu_mode_to_bits(mode);
	alu: proc_alu_netlist port map (
		clk => clk,
		rst => rst,
		en => en,
		mode => s_mode,
		status_in => status_in,
		a => a,
		b => b,
		result => result,
		status_out => status_out
	);
	
end Behavioral;

